上課摘要:
-- File Name : CH1_1_1.VHD
-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*********************************************
ENTITY ch1_1_1 IS
PORT(
pin48 : IN std_logic;
pin49 : IN std_logic;
pin7 : OUT std_logic
);
END ch1_1_1;
--*********************************************
ARCHITECTURE arch_a OF ch1_1_1 IS
BEGIN
pin7 <= pin48 and pin49;
END arch_a;
作業指定:
- 請設計一個三輸入或閘(OR Gate),輸入變數分別為IN_A, IN_B, IN_C, 輸出變數為OUT_A,專案名稱使用『d學號』。
![](/image/image_gallery?uuid=b55dfb7d-8ffb-4595-85ef-2e1046ba1367&groupId=391366&t=1384099366250)
![](/image/image_gallery?uuid=b23f2d64-129c-44bb-bda3-b57756c49124&groupId=391366&t=1384099361190)