上課摘要:
■ 真值表程式
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity true_table is
port (X : IN STD_LOGIC_VECTOR(2 downto 0);
Y : OUT STD_LOGIC );
end true_table;
architecture a of true_table is
begin
Y <= '1' when X="010" else
'1' when X="110" else
'0';
end a;
布林函數:
D = A’BC’ + ABC’
作業指定:
- 請設計一個四輸入組合電路,輸入變數分別為A, B, C, D,輸出變數為F,其中F(A, B, C, D) = Σ(0, 1, 4, 6, 7, 9, 11, 13, 15),專案名稱使用『d學號』。
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